1 / 1

Matrix-Vector Multiplication as a CUDA Kernel

Linear AlgebraGPU Programming

Medium

Compute the matrix-vector product on the GPU. Given a matrix $A$ of shape $(M, N)$ and a vector $x$ of length $N$ , produce an output vector $y$ of length $M$ where each entry is the dot product of one row of $A$ with $x$ :

y[i] = \sum_{j=0}^{N-1} A[i, j] \cdot x[j]

Shapes follow the pattern $(M, N) \cdot (N,) \to (M,)$ . The matrix $A$ is stored in row-major order, so element $A[i, j]$ lives at flat index $\texttt{A[i*N + j]}$ . All buffers are device pointers and all values are float32.

Loading visualization...

Examples

Input: A = [[1, 2, 3], [4, 5, 6]], x = [1, 1, 1], M = 2, N = 3

Output: [6, 15]

Row $0$ sums to $1+2+3=6$ ; row $1$ sums to $4+5+6=15$ .

Input: A = [[1, 0], [0, 1], [1, 1]], x = [2, 3], M = 3, N = 2

Output: [2, 3, 5]

Each row picks or sums the entries of $x$ , giving $2$ , $3$ , and $2+3=5$ .

Hint 1

Map blockIdx.x * blockDim.x + threadIdx.x to the output row index i, then guard with if (i < M).

Hint 2

Each output y[i] is an independent dot product, so a single thread can accumulate it in a register with a serial loop over j.

Hint 3

Read row-major elements as A[i * N + j] and multiply by x[j] inside the inner loop.

Requirements

Launch one thread per output row so each thread computes a single entry $y[i]$ .
Inside the kernel, run an inner loop over $j$ from $0$ to $N - 1$ to accumulate the dot product.
Index $A$ with the row-major formula $\texttt{A[i*N + j]}$ ; the harness allocates $A$ as a contiguous $M \cdot N$ buffer.
Do not change the $\texttt{solve}$ signature; the runner binds it to a fixed ctypes prototype.

Constraints

$1 \le M, N \le 4096$ .
$\texttt{A}$ , $\texttt{x}$ , $\texttt{y}$ are device pointers managed by the harness; do not allocate or copy them inside $\texttt{solve}$ .
Launch with $256$ threads per block and a 1D grid sized to cover $M$ output rows.
All buffers are float32.

Try Similar Problems

RMS Normalization as a CUDA KernelMedium Layer Normalization as a CUDA KernelMedium Matrix Multiplication as a CUDA KernelMedium Outer Product as a CUDA KernelEasy Matrix Addition as a CUDA KernelEasy Hadamard Product as a CUDA KernelEasy Matrix Transpose as a CUDA KernelEasy L1 Normalization as a CUDA KernelMedium Cosine Similarity as a CUDA KernelMedium CUDA Dot Product: Multi-Block ReductionMedium L2 Normalization as a CUDA KernelMedium Tiled Matrix Multiplication as a CUDA KernelHard

Matrix-Vector Multiplication as a CUDA Kernel

Linear AlgebraGPU Programming

Medium

y[i] = \sum_{j=0}^{N-1} A[i, j] \cdot x[j]

Loading visualization...

Examples

Input: A = [[1, 2, 3], [4, 5, 6]], x = [1, 1, 1], M = 2, N = 3

Output: [6, 15]

Row $0$ sums to $1+2+3=6$ ; row $1$ sums to $4+5+6=15$ .

Input: A = [[1, 0], [0, 1], [1, 1]], x = [2, 3], M = 3, N = 2

Output: [2, 3, 5]

Each row picks or sums the entries of $x$ , giving $2$ , $3$ , and $2+3=5$ .

Hint 1

Map blockIdx.x * blockDim.x + threadIdx.x to the output row index i, then guard with if (i < M).

Hint 2

Each output y[i] is an independent dot product, so a single thread can accumulate it in a register with a serial loop over j.

Hint 3

Read row-major elements as A[i * N + j] and multiply by x[j] inside the inner loop.

Requirements

Launch one thread per output row so each thread computes a single entry $y[i]$ .
Inside the kernel, run an inner loop over $j$ from $0$ to $N - 1$ to accumulate the dot product.
Index $A$ with the row-major formula $\texttt{A[i*N + j]}$ ; the harness allocates $A$ as a contiguous $M \cdot N$ buffer.
Do not change the $\texttt{solve}$ signature; the runner binds it to a fixed ctypes prototype.

Constraints

$1 \le M, N \le 4096$ .
$\texttt{A}$ , $\texttt{x}$ , $\texttt{y}$ are device pointers managed by the harness; do not allocate or copy them inside $\texttt{solve}$ .
Launch with $256$ threads per block and a 1D grid sized to cover $M$ output rows.
All buffers are float32.

Try Similar Problems

A =

Accepts: array

x =

Accepts: array

Examples

Requirements

Constraints

Kernel performance

Matrix-Vector Multiplication as a CUDA Kernel

Examples

Requirements

Constraints

Kernel performance