TensorTonic
Problems
Grouped Program-ID Matmul in Triton
Linear AlgebraGPU Programming
Hard

Reimplement tiled matmul with a 1D launch grid and a grouped program-ID remap so adjacent programs share AAA and BBB tiles and hit warm L2 lines. For each output entry:

C[i,j]=∑k=0K−1A[i,k]⋅B[k,j]C[i, j] = \sum_{k=0}^{K-1} A[i, k] \cdot B[k, j]C[i,j]=k=0∑K−1​A[i,k]⋅B[k,j]

The arithmetic is identical to the plain matmul. The single change: switch from a 2D grid to a 1D grid of the same total size, then derive (pid_m,pid_n)(\text{pid\_m}, \text{pid\_n})(pid_m,pid_n) from pid\text{pid}pid with a GROUP_SIZE_M\texttt{GROUP\_SIZE\_M}GROUP_SIZE_M constexpr so the schedule walks the output in MMM-major groups. This is exactly the pattern Triton's official matmul tutorial uses.

Why it matters: a strictly row-major or column-major linear schedule streams one matrix and re-reads the other from DRAM on every tile. Grouped scheduling reuses each loaded AAA row-block across the group and each BBB column-block across the same group, multiplying L2 hit rate by roughly GROUP_SIZE_M\texttt{GROUP\_SIZE\_M}GROUP_SIZE_M.

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Examples

Input: A = [[1, 2], [3, 4]], B = [[5, 6], [7, 8]]

Output: [[19, 22], [43, 50]]

Input: A = [[1, 0, 1], [0, 1, 0]], B = [[1, 2], [3, 4], [5, 6]]

Output: [[6, 8], [3, 4]]

Hint 1

Compute num_pid_in_group=GROUP_SIZE_M⋅num_pid_n\text{num\_pid\_in\_group} = \texttt{GROUP\_SIZE\_M} \cdot \text{num\_pid\_n}num_pid_in_group=GROUP_SIZE_M⋅num_pid_n, then group_id=pid/num_pid_in_group\text{group\_id} = \text{pid} / \text{num\_pid\_in\_group}group_id=pid/num_pid_in_group, and first_pid_m=group_id⋅GROUP_SIZE_M\text{first\_pid\_m} = \text{group\_id} \cdot \texttt{GROUP\_SIZE\_M}first_pid_m=group_id⋅GROUP_SIZE_M. Clamp the group height for the partial last group.

Hint 2

Inside the group, decode pid_m\text{pid\_m}pid_m and pid_n\text{pid\_n}pid_n so adjacent values of pid\text{pid}pid keep the same rows of AAA warm across consecutive programs.

Hint 3

Once the two program IDs are decoded, the rest of the kernel is identical to a standard 2D-grid matmul: same KKK-loop, same tl.dot\texttt{tl.dot}tl.dot, same masked store.

Requirements

  • Use a 1D launch grid of size ⌈M/BLOCK_M⌉⋅⌈N/BLOCK_N⌉\lceil M/\text{BLOCK\_M} \rceil \cdot \lceil N/\text{BLOCK\_N} \rceil⌈M/BLOCK_M⌉⋅⌈N/BLOCK_N⌉
  • Derive (pid_m,pid_n)(\text{pid\_m}, \text{pid\_n})(pid_m,pid_n) from the single program ID with the standard grouped remap
  • Mask the loads and stores on the MMM, NNN, and KKK tails; accumulate in fp32
  • The solve\texttt{solve}solve signature must not change
  • use ieee precision for consistent float32 accuracy across gpus.

Constraints

  • 1≤M,N,K≤7681 \le M, N, K \le 7681≤M,N,K≤768.
  • All tensors are torch.float32 on cuda.
  • Tolerance: atol=1e-2 + rtol=1e-2 * abs(expected) for K≥128K \ge 128K≥128 to absorb fp32 accumulation drift.
Try Similar Problems
Split-K Matmul in TritonHardBlock-Pointer Matmul in TritonMediumScaled Dot-Product Attention in TritonMediumAutotuned Matrix Multiplication in TritonMediumTiled Transpose in TritonMediumGEMV: Matrix Vector Product in TritonMediumFused Matmul + Bias + ReLU in TritonMediumTiled Matrix Multiplication in TritonMediumTiled Matrix Multiplication as a CUDA KernelHardScaled Dot-Product Attention in CUDAHardFused Tiled Matmul and ReLUHardVector Addition in TritonEasy

Accepts: array

Accepts: array

You must run your code first.

Kernel performance

Submit a correct solution to see your kernel performance.

Grouped Program-ID Matmul in Triton

Grouped Program-ID Matmul in Triton

Linear AlgebraGPU Programming
Hard

Reimplement tiled matmul with a 1D launch grid and a grouped program-ID remap so adjacent programs share AAA and BBB tiles and hit warm L2 lines. For each output entry:

C[i,j]=∑k=0K−1A[i,k]⋅B[k,j]C[i, j] = \sum_{k=0}^{K-1} A[i, k] \cdot B[k, j]C[i,j]=k=0∑K−1​A[i,k]⋅B[k,j]

The arithmetic is identical to the plain matmul. The single change: switch from a 2D grid to a 1D grid of the same total size, then derive (pid_m,pid_n)(\text{pid\_m}, \text{pid\_n})(pid_m,pid_n) from pid\text{pid}pid with a GROUP_SIZE_M\texttt{GROUP\_SIZE\_M}GROUP_SIZE_M constexpr so the schedule walks the output in MMM-major groups. This is exactly the pattern Triton's official matmul tutorial uses.

Why it matters: a strictly row-major or column-major linear schedule streams one matrix and re-reads the other from DRAM on every tile. Grouped scheduling reuses each loaded AAA row-block across the group and each BBB column-block across the same group, multiplying L2 hit rate by roughly GROUP_SIZE_M\texttt{GROUP\_SIZE\_M}GROUP_SIZE_M.

Loading visualization...

Examples

Input: A = [[1, 2], [3, 4]], B = [[5, 6], [7, 8]]

Output: [[19, 22], [43, 50]]

Input: A = [[1, 0, 1], [0, 1, 0]], B = [[1, 2], [3, 4], [5, 6]]

Output: [[6, 8], [3, 4]]

Hint 1

Compute num_pid_in_group=GROUP_SIZE_M⋅num_pid_n\text{num\_pid\_in\_group} = \texttt{GROUP\_SIZE\_M} \cdot \text{num\_pid\_n}num_pid_in_group=GROUP_SIZE_M⋅num_pid_n, then group_id=pid/num_pid_in_group\text{group\_id} = \text{pid} / \text{num\_pid\_in\_group}group_id=pid/num_pid_in_group, and first_pid_m=group_id⋅GROUP_SIZE_M\text{first\_pid\_m} = \text{group\_id} \cdot \texttt{GROUP\_SIZE\_M}first_pid_m=group_id⋅GROUP_SIZE_M. Clamp the group height for the partial last group.

Hint 2

Inside the group, decode pid_m\text{pid\_m}pid_m and pid_n\text{pid\_n}pid_n so adjacent values of pid\text{pid}pid keep the same rows of AAA warm across consecutive programs.

Hint 3

Once the two program IDs are decoded, the rest of the kernel is identical to a standard 2D-grid matmul: same KKK-loop, same tl.dot\texttt{tl.dot}tl.dot, same masked store.

Requirements

  • Use a 1D launch grid of size ⌈M/BLOCK_M⌉⋅⌈N/BLOCK_N⌉\lceil M/\text{BLOCK\_M} \rceil \cdot \lceil N/\text{BLOCK\_N} \rceil⌈M/BLOCK_M⌉⋅⌈N/BLOCK_N⌉
  • Derive (pid_m,pid_n)(\text{pid\_m}, \text{pid\_n})(pid_m,pid_n) from the single program ID with the standard grouped remap
  • Mask the loads and stores on the MMM, NNN, and KKK tails; accumulate in fp32
  • The solve\texttt{solve}solve signature must not change
  • use ieee precision for consistent float32 accuracy across gpus.

Constraints

  • 1≤M,N,K≤7681 \le M, N, K \le 7681≤M,N,K≤768.
  • All tensors are torch.float32 on cuda.
  • Tolerance: atol=1e-2 + rtol=1e-2 * abs(expected) for K≥128K \ge 128K≥128 to absorb fp32 accumulation drift.
Try Similar Problems
Split-K Matmul in TritonHardBlock-Pointer Matmul in TritonMediumScaled Dot-Product Attention in TritonMediumAutotuned Matrix Multiplication in TritonMediumTiled Transpose in TritonMediumGEMV: Matrix Vector Product in TritonMediumFused Matmul + Bias + ReLU in TritonMediumTiled Matrix Multiplication in TritonMediumTiled Matrix Multiplication as a CUDA KernelHardScaled Dot-Product Attention in CUDAHardFused Tiled Matmul and ReLUHardVector Addition in TritonEasy

Accepts: array

Accepts: array

You must run your code first.

Kernel performance

Submit a correct solution to see your kernel performance.

Problems
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