TensorTonic
Problems
L2 Vector Norm in Triton
Linear AlgebraGPU Programming
Easy

Compute the L2 (Euclidean) norm of a 1D float tensor in Triton. For a tensor xxx of length NNN, write the scalar norm into out[0]\texttt{out}[0]out[0]:

out[0]=∑i=0N−1x[i]2\texttt{out}[0] = \sqrt{\sum_{i=0}^{N-1} x[i]^2}out[0]=i=0∑N−1​x[i]2​

The reduction is a sum-of-squares; the square root is applied once on the host after the kernel returns. Each program reduces its tile in registers, combines partials via a single atomic per program on a scratch scalar, and the launcher takes the square root.

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Examples

Input: x = [3.0, 4.0]

Output: [5.0]

Input: x = [1.0, 2.0, 2.0]

Output: [3.0]

Hint 1

Square inside the tile, not afterwards. Fusing the multiply into the reduction with tl.sum(x * x)\texttt{tl.sum(x * x)}tl.sum(x * x) halves the register pressure.

Hint 2

Mask with other=0.0\texttt{other=0.0}other=0.0 so the tail lanes contribute zero. The square of zero is still zero, so no special handling at the boundary.

Hint 3

The square root is a single host op after the kernel: out.copy_(torch.sqrt(sumsq_buf))\texttt{out.copy\_(torch.sqrt(sumsq\_buf))}out.copy_(torch.sqrt(sumsq_buf)). Keep the per-lane work to the reduction only.

Requirements

  • Compute the sum of squares in a single pass, squaring lanes in registers before the reduction
  • Accumulate partials across programs with one atomic add per program on a scratch scalar
  • Apply the square root on the host after the kernel; do not square-root per lane in the kernel
  • Mask the tail so masked lanes contribute zero to the sum of squares
  • The solve\texttt{solve}solve signature must not change

Constraints

  • 1≤N≤1061 \le N \le 10^61≤N≤106.
  • Input tensor is torch.float32 on cuda and contiguous; output has shape (1,).
  • Inputs are bounded such that the sum of squares stays representable in float32 (no overflow).
  • Tolerance: combined atol=1e-2, rtol=1e-2 to absorb large-NNN accumulation drift.
Try Similar Problems
Vector Addition in TritonEasyFused Multiply-Add in TritonEasyVector Sum Reduction in TritonEasyVector Max Reduction in TritonEasyScaled Dot-Product Attention in TritonMediumBlock-Pointer Matmul in TritonMediumAutotuned Matrix Multiplication in TritonMediumTiled Transpose in TritonMediumGEMV: Matrix Vector Product in TritonMediumFused Matmul + Bias + ReLU in TritonMediumTiled Matrix Multiplication in TritonMediumOuter Product as a CUDA KernelEasy

Accepts: array

You must run your code first.

Kernel performance

Submit a correct solution to see your kernel performance.

L2 Vector Norm in Triton

L2 Vector Norm in Triton

Linear AlgebraGPU Programming
Easy

Compute the L2 (Euclidean) norm of a 1D float tensor in Triton. For a tensor xxx of length NNN, write the scalar norm into out[0]\texttt{out}[0]out[0]:

out[0]=∑i=0N−1x[i]2\texttt{out}[0] = \sqrt{\sum_{i=0}^{N-1} x[i]^2}out[0]=i=0∑N−1​x[i]2​

The reduction is a sum-of-squares; the square root is applied once on the host after the kernel returns. Each program reduces its tile in registers, combines partials via a single atomic per program on a scratch scalar, and the launcher takes the square root.

Loading visualization...

Examples

Input: x = [3.0, 4.0]

Output: [5.0]

Input: x = [1.0, 2.0, 2.0]

Output: [3.0]

Hint 1

Square inside the tile, not afterwards. Fusing the multiply into the reduction with tl.sum(x * x)\texttt{tl.sum(x * x)}tl.sum(x * x) halves the register pressure.

Hint 2

Mask with other=0.0\texttt{other=0.0}other=0.0 so the tail lanes contribute zero. The square of zero is still zero, so no special handling at the boundary.

Hint 3

The square root is a single host op after the kernel: out.copy_(torch.sqrt(sumsq_buf))\texttt{out.copy\_(torch.sqrt(sumsq\_buf))}out.copy_(torch.sqrt(sumsq_buf)). Keep the per-lane work to the reduction only.

Requirements

  • Compute the sum of squares in a single pass, squaring lanes in registers before the reduction
  • Accumulate partials across programs with one atomic add per program on a scratch scalar
  • Apply the square root on the host after the kernel; do not square-root per lane in the kernel
  • Mask the tail so masked lanes contribute zero to the sum of squares
  • The solve\texttt{solve}solve signature must not change

Constraints

  • 1≤N≤1061 \le N \le 10^61≤N≤106.
  • Input tensor is torch.float32 on cuda and contiguous; output has shape (1,).
  • Inputs are bounded such that the sum of squares stays representable in float32 (no overflow).
  • Tolerance: combined atol=1e-2, rtol=1e-2 to absorb large-NNN accumulation drift.
Try Similar Problems
Vector Addition in TritonEasyFused Multiply-Add in TritonEasyVector Sum Reduction in TritonEasyVector Max Reduction in TritonEasyScaled Dot-Product Attention in TritonMediumBlock-Pointer Matmul in TritonMediumAutotuned Matrix Multiplication in TritonMediumTiled Transpose in TritonMediumGEMV: Matrix Vector Product in TritonMediumFused Matmul + Bias + ReLU in TritonMediumTiled Matrix Multiplication in TritonMediumOuter Product as a CUDA KernelEasy

Accepts: array

You must run your code first.

Kernel performance

Submit a correct solution to see your kernel performance.

Problems
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